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? semiconductor components industries, llc, 2004 july, 2004 ? rev. 0 1 publication order number: ncv4279c/d ncv4279c 5.0 v micropower 150 ma ldo linear regulator with delay, adjustable reset , and monitor flag the ncv4279c is a 5.0 v precision micropower voltage regulator. the output current capability is 150 ma. the output voltage is accurate within 2.0% with a maximum dropout voltage of 0.6 v at 150 ma. low quiescent current is a feature drawing only 130 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset (with delay), and a flag monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. the use of the flag monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. the reset threshold voltage can be decreased by the connection of an external resistor divider to r adj lead. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. the device has also been optimized for emc conditions. features ? 5.0 v 2.0% output ? low 130 a quiescent current ? active reset ? adjustable reset ? 150 ma output current capability ? fault protection ? +60 v peak transient voltage ? ?15 v reverse voltage ? short circuit ? thermal overload ? early warning through flag /mon leads ? internally fused leads in so?14 package ? ncv prefix for automotive and other applications requiring site and control changes http://onsemi.com so?14 d suffix case 751a 1 14 pin connections flag reset v out nc gnd gnd gnd gnd 114 gnd gnd v in delay mon r adj marking diagrams 1 ncv4279c awlyww 14 a = assembly location wl, l = wafer lot y = year ww, w = work week so?14 so?8 d suffix case 751 1 8 1 4279c alyw 8 gnd delay 18 reset r adj flag mon v out v in so?8 ordering information see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
ncv4279c http://onsemi.com 2 v out gnd v in r adj ncv4279c 10 f 10 k r rst reset 10 f microprocessor delay c delay v bat v dd flag figure 1. application diagram mon r flg 10 k i/o i/o maximum ratings 2 rating value unit v in (dc) ?15 to 45 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v operating voltage 45 v v out (dc) 16 v voltage range (reset , flag ) ?0.3 to 10 v input voltage range (mon) ?0.3 to 10 v esd susceptibility (human body model) 2.0 kv junction temperature, t j ?40 to +150 c storage temperature, t s ?55 to 150 c package thermal resistance, so?8: junction?to?case, r jc junction?to?ambient, r ja 45 165 c/w package thermal resistance, so?14 (fused) minimum pad data: junction?to?case, r jc junction?to?ambient, r ja junction?to?pin, r jp (note 3) 15 110 33 c/w lead temperature soldering: reflow: (smd styles only) (notes 1, 2) 240 peak c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 2during the voltage range which exceeds the maximum tested voltage of v in , operation is assured, but not specified. wider limits may apply. thermal dissipation must be observed closely. 1. 60 second maximum above 183 c. 2. ?5 c/+0 c allowable conditions. 3. measured to pin 4, with pins 3, 4, 5, 10, 11 and 12 soldered to a thermal plane.
ncv4279c http://onsemi.com 3 electrical characteristics (i out = 1.0 ma, ?40 c t j 125 c; 6.0 v < v in < 26 v; unless otherwise specified.) characteristic test conditions min typ max unit output stage output voltage 9.0 v < v in < 16 v, 100 a i out 150 ma 6.0 v < v in < 26 v, 100 a i out 150 ma 4.90 4.85 5.0 5.0 5.10 5.15 v v dropout voltage (v in ? v out ) i out = 150 ma i out = 100 a ? ? 400 100 600 150 mv mv load regulation v in = 14 v, 5.0 ma i out 150 ma -30 5.0 30 mv line regulation [v out (typ) + 1.0] < v in < 26 v, i out = 1.0 ma ? 15 60 mv quiescent current, (i q ) active mode i out = 100 a, v in = 12 v, delay = 3.0 v, mon = 3.0 v i out = 75 ma, v in = 14 v, delay = 3.0 v, mon = 3.0 v i out 150 ma, v in = 14 v, delay = 3.0 v, mon = 3.0 v ? ? ? 130 4.0 12 200 6.0 19 a ma ma current limit ? 151 300 ? ma short circuit output current v out = 0 v 40 190 ? ma thermal shutdown (guaranteed by design) 150 180 ? c reset function (reset) reset threshold high (v rh ) low (v rl ) v out increasing v out decreasing 4.55 4.50 4.70 4.60 0.98 v out 0.97 v out v v output voltage low (v rlo ) 1.0 v v out v rl , r reset = 10 k ? 0.1 0.4 v delay switching threshold (v dt ) ? 1.4 1.8 2.2 v lower delay switching threshold (v ld ) ? 0.3 0.45 0.6 v reset delay low voltage v out < reset threshold low(min) ? ? 0.1 v delay charge current delay = 1.0 v, v out > v rh 6.0 9.0 15 a delay discharge current delay = 1.0 v, v out = 1.5 v 5.0 ? ? ma reset adjust switching voltage (v r(adj) ) ? 1.23 1.31 1.39 v flag /monitor monitor threshold increasing and decreasing 1.10 1.20 1.31 v hysteresis ? 20 50 100 mv input current mon = 2.0 v ?0.5 0.1 0.5 a output saturation voltage mon = 0 v, i flag = 1.0 ma ? 0.1 0.4 v
ncv4279c http://onsemi.com 4 package pin description package pin number so?8 so?14 pin symbol function 3 1 r adj reset adjust. if not needed connect to ground. 4 2 delay timing capacitor for reset function. 5 3?5, 10?12 gnd ground. all gnd leads must be connected to ground . ? 6 nc no connection. 6 7 reset active reset (accurate to v out 1.0 v) 7 8 flag open collector output from early warning comparator. 8 9 v out 2.0%, 150 ma output. 1 13 v in input voltage. 2 14 mon monitor. input for early warning comparator. if not needed connect to v out. typical performance characteristics ?40 v out (v) 4.98 temperature ( c) 4.99 5.00 5.01 ?25 ?10 125 5 203550658095110 v out = 5.0 v v in = 14 v i out = 5.0 ma figure 2. output voltage vs. temperature figure 3. quiescent current vs. output current figure 4. quiescent current vs. output current +25 c ?40 c 0 i q (ma) 0 i out (ma) 0.2 0.4 0.6 0.8 1.0 1.2 5 10152025 +125 c v in = 12 v 0 i q (ma) 0 i out (ma) 2 4 6 8 10 12 14 15 30 45 60 140 75 90 105 120 135 +25 c ?40 c +125 c v in = 12 v 6 i q (ma) 0 v in (v) 1 2 3 4 5 6 7 8101214 26 16 18 20 22 24 i out = 10 ma i out = 50 ma i out = 100 ma t = 25 c figure 5. quiescent current vs. input voltage
ncv4279c http://onsemi.com 5 typical performance characteristics figure 6. quiescent current vs. input voltage i q ( a) v in (v) +25 c ?40 c +125 c 0 dropout voltage (mv) 0 i out (ma) 150 200 250 300 350 400 450 25 50 75 100 150 50 100 125 figure 7. dropout voltage vs. output current 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100110120130140150 unstable region stable region c vout = 10 f figure 8. output capacitor esr esr ( ) output current (ma) figure 9. output stability with output capacitor change 0.01 0.1 1 10 100 1000 0 102030 5060708090100110 output current (ma) esr ( ) c vout = 10 f c vout = 0.1 f unstable region stable region 40 i out = 100 a t = 25 c 120 125 130 135 140 145 150 6 1014182226
ncv4279c http://onsemi.com 6 v in reset v out flag r adj delay figure 10. block diagram gnd mon current source (circuit bias) current limit sense error amplifier v bg i bias v bg v bg i bias i bias v bg i bias + ? + ? + ? + ? + bandgap reference thermal protection 1.8 v 3.0 a
ncv4279c http://onsemi.com 7 circuit description figure 11. reset and delay circuit wave forms v in 1.8v v dt v out delay reset reset threshold td 0.45v v ld td power on reset input v dip under?voltage secondary spike output overload regulator control functions the ncv4279c contains a microprocessor?compatible control function reset (figure 11). reset function a reset signal (low voltage) is generated as the ic powers up. after v out increases above the reset threshold, the delay timer is started. when the delay timer passes 1.8 v, the reset signal goes high. a discharge of the delay timer is started when v out drops and stays below the reset threshold. when the delay timer level drops below 0.45 v, the reset signal is brought low. the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic thereby guaranteeing that the reset signal is valid for v out as low as 1.0 v. adjustable reset function the reset threshold can be made lower by connecting an external resistor divider to the r adj lead from the v out lead, as displayed in figure 12. this lead is grounded to select the default value of 4.6 v. figure 12. adjustable reset r adj to p and system power r rst v out c out reset c delay delay ncv4279c to p and reset port delay function the reset delay circuit provides a delay (programmable by external capacitor) on the reset output lead. the delay lead provides source current (typically 2.5 a) to the external delay capacitor at the following times: 1. during power up (once the regulation threshold has been exceeded). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is discharged when the regulation (reset threshold) has been violated. when the delay capacitor discharges to 0.45 v, the reset signal pulls low. flag /monitor function an on?chip comparator is available to provide an early warning to the microprocessor of a possible reset signal. the reset signal typically turns the microprocessor off instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the flag pin will allow the microprocessor time to complete its present task before shutting down. this function is performed by a comparator referenced to the bandgap voltage. the actual trip point can be programmed externally using a resistor divider to the input monitor (mon) (figure 13). the typical threshold is 1.20 v on the mon pin. figure 13. flag /monitor function v bat v in mon v out c out v cc i/o reset p flag reset gnd delay ncv4279c r adj
ncv4279c http://onsemi.com 8 application notes flag monitor figure 14 shows the flag monitor waveforms as a result of the circuit depicted in figure 13. as the output voltage falls (v out ), the monitor threshold is crossed. this causes the voltage on the flag output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t warning is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. figure 14. flag monitor circuit waveform v out mon reset flag monitor ref. voltage t warning flag setting the delay time the delay time is controlled by the reset delay low voltage, delay switching threshold, and the delay charge current. the delay follows the equation: t delay [ c delay (v dt reset delay low voltage) ] delay charge current example: using c delay = 33 nf. use the typical value for delay low voltage = 0.45 v. use the typical value for v dt = 1.8 v. use the typical value for delay charge current = 2.5 a. t delay [ 33 nf(1.8 0.45 v) ] 2.5 a 17.8 ms stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer's data sheet usually provides this information. the value for the output capacitor c out shown in figure 15 should work for most applications, but is not necessarily the optimized solution. figure 15. test and application circuit showing output compensation v in v out c out ** 10 f r rst reset c in * 0.1 f ncv4279c *c in required if regulator is located far from the power supply filter. **c out required for stability. capacitor must operate at minimum temperature expected. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 16) is: p d(max) [v in(max) v out(min) ]i out(max) (1) v in(max) i q where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? i q control features i out i in figure 16. single output regulator with key performance parameters labeled v in v out }
ncv4279c http://onsemi.com 9 heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heat sink manufacturers. further mounting and cooling information is available in the application note, an1040/d, amounting considerations for power semiconductorso located in the on semiconductor web site. thermal, mounting, and heatsinking are discussed in the on semiconductor applications note an1040/d.
ncv4279c http://onsemi.com 10 ordering information device output voltage package shipping 2 ncv4279cd1 so 8 98 units / rail NCV4279CD1R2 50v so?8 2500 / tape & reel ncv4279cd2 5.0 v so 14 55 units / rail ncv4279cd2r2 so?14 2500 / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv4279c http://onsemi.com 11 package dimensions so?8 d suffix case 751?07 issue ab seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 soldering footprint
ncv4279c http://onsemi.com 12 package dimensions so?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncv4279c/d smart regulator is a registered trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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